M.Tech Student at Indian Institute of Technology, Roorkee. Before IIT Roorkee I have completed 1^st year of M.Tech in Microelectronics at Indian Institute of Information Technology, Allahabad . I have done my B.Tech from National Institute of Technology, Raipur in 2020. I want to work in Semiconductor or Telecomm industry.

EDUCATION

IIT Roorkee

MTech - Communication Systems

2021-2023

GPA : 7.57

NIT Raipur

BTech - Electronics and Telecommunication

2016-2020

GPA : 7.37

St. Joseph's School

Higher Secondary

2015-2016

81.80 %

St. Joseph's School

High School

2013-2014

90.33 %

SKILLS

C++

DataStructure

Verilog

MATLAB

LTspice

Xilinx

HTML

CSS

INTERNSHIP & TRAINING

Summer Intern

NIT Raipur

[May 2019 - Jul 2019]

Network Optimization:

Work on different algorithms for shortest path finding from a graph for a certain problem.
Based on results, optimized different networks.
Simulated Intel lab view problem for 54 nodes in MATLAB with the help of clustering.

Vocational Training

Doordarshan Kendra Raipur

[Jun 2018 - Jun 2018]

TV Transmission, Studio Equipment and Earth Station.

Vocational Training

Bhilai Steel Plant (SAIL)

[May 2018 - Jun 2018]

Telephone Exchange and Substations.

PROJECTS

Structural Massive Access for Scalable Cell-Free Massive MIMO

[May 2022 - Present]

Working on scalable cell-free mMIMO project which can meet the demand for increasing number of users, higher data rates, and stringent quality-of-service (QoS) in the beyond fifth generation (B5G) networks.
Due to structured pilot assignment, pilot contamination can be avoided, results higher spectral efficiency.

32 Bits MIPS (RISC) Single Cycle Processor

[Jul 2022 - Aug 2022]

Simulated single cycle MIPS processor using Verilog in Xilinx VIVADO software.
Verified the R-Type, I-Type and J-Type instructions result.

Intelligent Reflecting Surface vs Decode-and-Forward Relay

[Jan 2022 - May 2022]

Compared IRS (Intelligent Reflecting Surfaces) with DF (Decode and Forward) relaying in terms of minimum transmit power requirements and maximum energy efficiency.
Computed minimum number elements (N_min) required in IRS to beat DF for achieving higher data rate than DF.
After assuming ideal scenario for IRS, obtained N_min = 164 for rate = 4 bits/sec/Hz and N_min = 74 for rate = 6 bits/sec/Hz.

Compact User-Specific Reconfigurable Intelligent Surfaces

[Jan 2022 - May 2022]

Uplink transmission by Reconfigurable intelligent surface (RIS) with multilayer concept have reduced the size, cost and power constraints at the user side for large scale antenna array requirement in next-generation wireless communications.
Multi-layer US-RIS can also be partially controlled, which brings about a new degree of freedom (DoF) for beamformer design that can be beneficially exploited for performance enhancement.

Implemented Bandgap Reference Circuit using LTspice

[Mar 2021 - Apr 2021]

Implemented BGR circuit using different topologies:
1. Current mirror
2. Current mirror with the starter circuit
3. Op-Amp
4. Op-Amp with the starter circuit

Obtained V_ref = 0.9 V and Temperature Coefficient <= 50ppm/^oC

Resume Webpage

[Feb 2021 - Mar 2021]

Built a resume web-page using HTMLand CSS.
Learned basics of HTML and CSS.

An Ultrasonic Navigation System for Blind People

[Aug 2019 - Dec 2019]

This project is to investigate the development of a navigation aid for blind and visually impaired people.
It was based on a Microcontroller (Arduino UNO), This aid is portable and gives information to the user with the help of different intensity of vibration and ultrasound.

CONTACT

Get in Touch

My Address

Near Boys Hostel Block Colony Pamgarh, Chhattisgarh, India